The present invention relates to digital data processing, and in particular to hardware emulators used in the development of digital data processing devices.
The programmable digital processor, which executes instructions of a stored program in a digital device, has become a ubiquitous instrument. A modern computer system typically comprises one or more central processing units (CPU) which execute the instructions of an operating system and user application software. It usually also includes numerous auxiliary processors which perform special functions, such as control of input/output channels, control of data storage devices, control of keyboards or other input devices, control of displays, etc. Although usually associated with computers, programmable processors are increasingly found in medical instruments, kitchen appliances, automobiles, cell phones, manufacturing apparatus, and a variety of other devices. Indeed, as prices have declined and capabilities have increased, there seems to be no end to the uses to which processors are being put.
Although small, a modem programmable processor is a device of enormous complexity. A processor typically contains data registers, special registers, arithmetic/logic units, instruction decoder and sequencer, internal data buses, control logic, and I/O ports, and may also contain on-board cache for instructions or data, and various other elements. By cramming more and more such elements onto a single chip, the capability of a processor can be enhanced. With the demands of the marketplace, there is a need for ever faster and more powerful processors. This, of course, increases the complexity of the devices and places greater demand on the developers of processor hardware.
Because the design and development of a processor is a task of great complexity, developers have long used computers and similar digital devices in the development of processors. In particular, one of the design tools used for the development of processors and other complex digital logic devices is the hardware emulator.
A hardware emulator is a device which mimics the behavior of a processor, a component of a processor, or other digital logic based on a detailed design specification, without the actual physical processor being built. I.e., a detailed design specification of a processor is used as a blueprint for configuring a special-purpose emulation device, which then acts exactly as the processor would. I.e., the configured emulator responds to inputs in exactly the way the proposed processor would. Because the emulator is in fact a special-purpose device configured to act like the processor, rather than a finished processor, it can""t match the speed of a real processor, nor will it necessarily be able to detect all design problems. However, it is a very useful tool in digital logic design, and is often used to verify the functional correctness of a complex design before constructing an actual device.
One type of known hardware emulator is based on an array of large field programmable gate arrays (FPGA). The FPGA emulator typically contains many logic gates with a large set of configurable interconnections. The system is configured to emulate a logic network by specifying the interconnections between programmable cells. While this system works well for small logic networks, it does not scale particularly well. The number of interconnections required to provide full interconnection of any arbitrary gate with any other gate grows as the square of the number of gates. Most large FPGA systems therefore do not provide full interconnections, i.e., there are only a limited number of inputs to each cell, and it is not always possible to route an output of one cell directly to an input of another cell.
An alternative type of hardware emulator is a time-multiplexed array of emulation processor cells. In the time-multiplexed design, each cell is in fact a small processor which executes a control program to emulate a different logic function at each respective clock cycle. All cells run off a single synchronous system clock. Thus, the time-multiplexed processor array requires some integral number of clock cycles, N, for its cells to cover all the logic functions of the design. Each cell in the time-multiplexed system is reused each clock cycle to perform the function that would require at least N cells in the FPGA array.
Naturally, the time-multiplexed processor array emulator is much slower than an FPGA array covering an equivalent number of logic functions. The speed of the time-multiplexed emulator is a major drawback to its use. However, it is difficult to construct FPGA emulators sufficiently large to emulate complex logic designs. Not only does the FPGA require at least one cell for each emulated logic function, but because there are only a limited number of interconnections, it is not generally possible to use all the cells in an FPGA. This problem grows with the complexity of the logic design, so that as the number of logic functions to emulate increases, the percentage of cells in an FPGA which can not be used also increases. Because the time-multiplexed processor array re-uses its cells and cell interconnections over and over again, it is more flexible and has the potential to emulate far more complex designs than the non-time-multiplexed FPGA emulator.
As digital logic designs increase in complexity, there is a need for improved emulators to support the development effort, which overcome the drawbacks of the existing art time-multiplexed processor array emulators and FPGA emulators.
A hardware emulator contains multiple emulation chips, each chip containing an array of cells, and a programmable interconnection array. Each cell performs only a single logic function, which is programmable to configure the emulator. The cells are enabled by a sequential wave signal, which enables successive subsets (logical rows) of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input
In the preferred embodiment, the chip contains an array of Sxc3x97P cells arranged in S rows (subsets) of P cells each, each row being enabled by a separate wave of wave generation logic. A set of P output pairs (each containing a data line and a strobe line) corresponds to the P cells of each row. On the step enable pulse of row I, cell J may output using output pair J. In fact, there are two sets of P output pairs, one for use in communicating with other chips on the same circuit card, and the other for communicating with more remote chips. There are similarly two sets of P input pairs.
In the preferred embodiment, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. Thus it is possible to output an off-chip signal from or receive an off-chip signal into any cell in the chip, although the number of ports is related to the number of columns P, and not the number of rows S.
In a first preferred embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave generated by the wave logic. The first embodiment greatly reduces the number of interconnection switches, but each switch is more complex and has the potential to slow down the emulator.
In a second preferred embodiment, fill interconnection of cells within a chip is provided by providing a programmable array of interconnect switches. The switches are programmed when the emulator is configured.
The hardware emulator described herein may thus be viewed as a hybrid of the FPGA type emulator and the time-multiplexed processor array emulator. Individual cells are very simple and operate very quickly, resembling in behavior the FPGA emulator cells. However, the interconnects behave more like the time-multiplexed array model, providing greater interconnection and the ability to emulate more complex designs than is typically possible with the FPGA emulator.
The details of the present invention, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts, and in which: